The present invention relates to a sync signal generator circuit for use in visual equipment such as a display apparatus and a recording/reproducing apparatus, and particularly relates to a sync signal generator circuit for generating a sync signal with a stable period.
In general, the sync signal that is used for displaying an image or recording image data in visual equipment is required to have a stable period. However, if the input is in a loss-of-signal state, no sync signal is detected. Further, when TV waves received by an antenna are very weak or immediately after a receiving channel is switched, a period of the sync signal may be temporarily disturbed. For this reason, Japanese Patent Kokai Publication No. 02-177681 published on Jul. 10, 1990 (corresponding to Japanese Patent No.2,584,309), for instance, proposes a method of generating a sync signal with a stable period even if a period of the input sync signal is disturbed. FIG. 10 is a block diagram showing the prior art sync signal generator circuit disclosed in this publication.
In FIG. 10, a reference numeral 22 denotes an input terminal to which a vertical sync signal is inputted, 23 denotes a differentiation circuit for the input vertical sync signal, 24 denotes a gate signal generator, 25 denotes a reset signal generator, and 26 denotes a counter. The differentiation circuit 23 detects a reference edge (namely, a leading edge) of the vertical sync signal inputted to the input terminal 22, thereby outputting a pulse corresponding to the reference edge. The gate signal generator 24 generates a gate signal on the basis of the output of the differentiation circuit 23 and the outputs of a second comparator 30, a third comparator 31, and a loss-of-signal detector 32, which will be described later. The reset signal generator 25 generates reset pulses on the basis of the outputs of the gate signal generator 24, the differentiation circuit 23, and a first comparator 29, which will be described later. The counter 26 counts clock pulses, and resets the counted value when it receives the reset pulse outputted from the reset signal generator 25.
Furthermore, in FIG. 10, a reference numeral 27 denotes a terminal, and 28 denotes a free-running period selector. To the terminal 27 four control parameters are inputted. The four control parameters consist of the two different parameters that determine timings of opening and closing a gate (not shown) of the reset signal generator 25 and the other two different parameters that determine the free-running period of the output sync signal. The free-running period selector 28 selects either of the two different free-running periods inputted to the terminal 27 in accordance with the output of the loss-of-signal detector 32, which will be described later.
Moreover, in FIG. 10, a reference numeral 29 denotes the first comparator, 30 denotes the second comparator, 31 denotes the third comparator, 32 denotes the loss-of-signal detector, 33 denotes an output control circuit, and 34 denotes an output terminal for the output vertical sync signal. The first comparator 29 compares the output of the counter 26 with the free-running period selected by the free-running period selector 28. The second comparator 30 compares the output of the counter 26 and one of the parameters inputted to the terminal 27 to detect the timing of closing the gate. The third comparator 31 compares the output of the counter 26 and one of the parameters inputted to the terminal 27 to detect the timing of opening the gate. The loss-of-signal detector 32 detects the state of the input vertical sync signal inputted to the input terminal 22 on the basis of the outputs of the differentiation circuit 23 and the first comparator 29. The output control circuit 33 prevents the vertical sync signal having too short period from being generated on the basis of the outputs of the reset signal generator 25, the first comparator 29, and the second comparator 30.
The sync signal generator circuit shown in FIG. 10 works as described below. The differentiation circuit 23 outputs a pulse each time a reference edge of the input vertical sync signal is detected. The gate signal that is outputted from the gate signal generator 24 becomes at a high level after the third comparator 31 detects the timing of opening the gate. Further, the gate signal becomes at a low level after the output of the differentiation circuit 23 goes high, after the second comparator 30 detects the timing of closing the gate thereby bringing its output high, or after the loss-of-signal detector 32 detects a loss-of-signal state thereby bringing its output high. If the output of the gate signal generator 24 is at a low level, the reset signal generator 25 closes the gate and inhibits passage of the output of the differentiation circuit 23. If the output of the gate signal generator 24 is at a high level, the reset signal generator 25 opens the gate and allows passage of the output of the differentiation circuit 23, thereby sending it to the counter 26 as a reset pulse of the counter 26. In addition, the reset signal generator 25 generates a reset pulse also when the first comparator 29 detects that the counted value of the counter 26 reaches a value corresponding to a free-running period selected by the free-running period selector 28.
Of the four parameters inputted to the terminal 27, the two different parameters that determine the period of the output sync signal correspond to a vertical period specified in the television signal standard and a little longer period, respectively. The free-running period selector 28 selects the vertical period specified in the standard if the loss-of-signal detector 32 detects a loss-of-signal state, thereby outputting a high level signal. Further, the free-running period selector 28 selects the period a little longer than the vertical period specified in the standard if the loss-of-signal detector 32 outputs a low level signal. The loss-of-signal detector 32 contains shift registers. When the output of the differentiation circuit 23 goes high, a high value is loaded into the first-stage shift register of the loss-of signal detector 32. Further, when the first comparator 29 detects that the counted value of the counter 26 reaches a value corresponding to the free-running period selected by the free-running period selector 28, a low value is loaded into the first-stage shift register. Each time a new value is loaded into the first-stage shift register, the values held in the respective shift registers are shifted to the next-stage registers at the same time. Accordingly, if the loss-of-signal state continues for a certain period, values of all shift registers become high. The output of the loss-of-signal detector 32 goes high if all the values of the shift registers are high, and goes low at the other times. The output control circuit 33 inhibits passage of the reset pulse outputted from the reset signal generator 25 between the instant when the first comparator 29 detects that the counted value of the counter 26 reaches a value corresponding to the free-running period selected by the free-running period selector 28 and the instant when the gate is closed by the gate signal generator 24.
The prior art vertical sync signal generator circuit as described above can suppress the generation of a vertical sync signal having too long or short period, thereby generating a vertical sync signal having a stable period even in the loss-of-signal state.
FIGS. 11A to 11D are timing charts indicating the output of the differentiation circuit 23, the counted value of the counter 26, the gate signal generated by the gate signal generator 24, the reset pulses generated by the reset signal generator 25, the output of the loss-of-signal detector 32, and the vertical sync signal outputted from the output terminal 34.
FIG. 11A shows a case where the sync signal generator circuit prevents the output vertical sync signal having too short period from being outputted even when the input vertical sync signal having too short period is inputted to the input terminal 22. In FIG. 11A, a symbol T1 denotes a period between the instant when the output of the differentiation circuit 23 goes high and the instant when the gate of the reset signal generator 25 opens (namely, when the gate signal generated by the gate signal generator 24 goes high). The gate opens when the counted value of the counter 26 reaches N1. While the gate is closed (namely, the gate signal is at a low level), the output of the differentiation circuit 23 cannot pass through the reset signal generator 25 so that no reset pulse is generated and the output vertical sync signal having too short period does not appear at the output terminal 34.
FIG. 11B shows a case where the output vertical sync signal having a free-running period is generated when the period of the input vertical sync signal temporarily becomes too long. In FIG. 11B, a symbol T2 denotes a little longer period than the vertical period specified in the standard. While the input vertical sync signal is periodically inputted to the input terminal 22, the output of the loss-of-signal detector 32 is at a low level, so that the free-running period selected by the free-running period selector 28 becomes T2, which is a little longer than the vertical period specified in the standard. Meanwhile, the counted value of the counter 26 is set to N2, and when the first comparator 29 detects this timing, the reset signal generator 25 generates a reset pulse. In addition, a symbol T3 denotes a period between the instant when the counter 26 counts the value N2 and the instant when the gate signal generator 24 closes the gate in accordance with the output of the second comparator 30. Further, a symbol t denotes a certain period longer than the period T3. The input vertical sync signals within the period T3 after a free-running vertical sync signal is generated are blocked by the output control circuit 33 and do not appear at the output terminal 34.
FIG. 11C shows a case where the output sync signal having the free-running period is generated if no input sync signal is inputted to the input terminal 22, establishing the loss-of-signal state. In FIG. 11C, a symbol T4 denotes a period corresponding to the vertical period specified in the standard. If the loss-of-signal detector 32 uses a four-bit shift register, all the values of the shift register go high and the output of the loss-of-signal detector 32 goes high when the sync signals having the free-running period are generated four times while no vertical sync signal is inputted. After that, the free-running period selected by the free-running period selector 28 changes from T2 to T4.
FIG. 11D shows a case where the output vertical sync signal outputted from the output terminal 34 is brought into synchronization with the input vertical sync signal when the input vertical sync signal begins to be inputted to the input terminal 22 during the loss-of-signal state. When the input sync signal is inputted to the input terminal 22, the output of the loss-of-signal detector 32 goes low, and the free-running period selector 28 accordingly changes the free-running period from T4 to T2. Because the period T2 corresponds to a period a little longer than the vertical period specified in the standard, if the period of the input sync signal inputted to the input terminal 22 is close to the period T4, the output of the differentiation circuit 23, which was originally blocked by the gate signal generated by the gate signal generator 24, appears while the gate signal is in the open state after an appropriate period, establishing the synchronization between the input sync signal and the output sync signal.
The above-described sync signal generator circuit, however, is designed under the assumption that it is applied to some limited standards such as an NTSC and a PAL. Therefore, it is difficult to apply the above-described sync signal generator circuit to an input sync signal having a wide variety of vertical periods, namely, a variety of video signal formats which use non-standard signals not conforming to the above-mentioned standards.
To cover a wide range of vertical period, a period T1 between the instant when the output of the differentiation circuit 23 goes high and the instant when the gate opens the gate must be short, and the free-running period T2must belong. By doing this, even if an input sync signal having a period close to the period T1 is inputted, the vertical period temporarily changes widely to be the same as the free-running period T2 when the sync signal generator circuit enters the free-running state. On the contrary, even if a vertical sync signal having a period close to the free-running period T2 is temporarily disturbed to have a period close to the period T1, an output sync signal having a short period is directly outputted from the output terminal 34 because the gate is in the open state meanwhile, resulting in the large fluctuation of the period in the output sync signal.
On the other hand, if the period T1 is increased and the free-running period T2 is decreased to obtain a stable vertical period, a wide range of vertical period cannot be simply covered, so that it is necessary to identify the format of an input video signal by some means and to reset the control parameter inputted to the terminal 27 to an appropriate value in accordance with the result of determination. However, it is generally difficult to accurately discriminate among all formats if an infinite number of non-standard signals are included. For instance, if the period of the input sync signal inputted to the input terminal 22 and the period T2 are set to almost the same values because of a wrong format determination or if the period T2 has to be minimized to obtain a very stable vertical period, the input sync signal and the output sync signal have almost the same period, as shown in FIG. 11D, so that it takes a very long time for the synchronizing process, in which the input sync signal and the output sync signal are synchronized.
It is an object of the present invention to provide a sync signal generator circuit which can generate a sync signal having a stable period and which can be applied to a wide variety of input sync signals.
According to the present invention, a sync signal generator circuit which receives a first sync signal to generate a second sync signal, comprises a first counter which counts predetermined clock pulses to output a counted value and which resets the counted value of the first counter each time the first counter detects a reference edge of the first sync signal; a first register which holds a first value Ni which is the counted value of the first counter immediately before the first counter is reset; a reset signal generator which generates a reset pulse; a second counter which counts predetermined clock pulses to output a counted value and which resets the counted value of the second counter each time the second counter receives the reset pulse; a second register which holds a second value No which is the counted value of the second counter immediately before the second counter is reset; and a sync pulse generator which generates the second sync signal on the basis of the reset pulse. The reset signal generator generates the reset pulse each time the counted value of the second counter matches a predetermined value Np or each time the first counter detects the reference edge of the first sync signal while an absolute value of a difference between the counted value of the second counter and the second value No is not greater than a predetermined permissible value Nj of a period fluctuation of the second sync signal, the predetermined value Np being equal to a reference value Nr if the reference value Nr which is predetermined on the basis of the first value Ni, is equal to the second value No, the predetermined value Np being greater than the second value No and not greater than a value No+Nj if the reference value Nr is greater than the second value No, the predetermined value Np being not smaller than a value Noxe2x88x92Nj and smaller than the second value No if the reference value Nr is smaller than the second value No.
Further, the reset signal generator may comprise a timing signal generator which generates a timing pulse on the basis of the reference edge of the first sync signal and the counted value of the second counter; a gate signal generator which generates a gate signal, the gate signal being in an open state from the instant when the counted value of the second counter becomes not smaller than a predetermined value to the instant when the reset signal generator generates the reset pulse, the gate signal being in a close state at the other times; and a gate circuit which allows passage of the timing pulse as the reset pulse when the gate signal is in the open state and which inhibits passage of the timing pulse when the gate signal is in the close state.
Furthermore, the sync signal generator circuit may comprise a mode discrimination circuit, which outputs a first mode discrimination signal if the first value Ni is kept to be not smaller than a predetermined lower-limit value Na and smaller than a predetermined upper-limit value Nb throughout a first predetermined period, outputs a second mode discrimination signal if the first value Ni is kept to be smaller than the lower-limit value Na or not smaller than the upper-limit value Nb throughout a second predetermined period, and continues outputting the immediately preceding discrimination signal at the other conditions. If the mode discrimination circuit is outputting the second mode discrimination signal, the reset signal generator generates no reset pulse even when the first counter detects the reference edge of the first sync signal while the absolute value of the difference between the counted value of the second counter and the second value No is not greater than the predetermined permissible value Nj.
Moreover, the sync signal generator circuit may comprise an external circuit which changes the lower-limit value Na and the upper-limit value Nb on the basis of the first value Ni.
In addition, the reference value Nr is set to Ni+Nj or Nixe2x88x92Nj when the mode discrimination circuit is outputting the first mode discrimination signal, and the reference value Nr is set to a predetermined free-running period value Nf when the mode discrimination circuit is outputting the second mode discrimination signal.
Further, the sync signal generator circuit may comprise an external circuit which changes the free-running period value Nf on the basis of the first value Ni.
Furthermore, the reference value Nr is set to a value greater than the first value Ni and smaller than Ni+Nj if the first value held in the first register is equal to the second value held in the second register or if the generation of the reset pulse by the reset signal generator results from the detection of reference edge of the first sync signal.
Moreover, the sync signal generator circuit may comprise a noise masking circuit which selectively allows passage of the reference edge of the first sync signal. The noise masking circuit obstructs the passage the reference edge of the first sync signal when the counted value of the first counter is not greater than a predetermined value. The reset of the first counter is performed on the basis of the reference edge of the first sync signal which has passed through the noise masking circuit.
In addition, the sync signal generator circuit may comprise a phase detector which detects whether the reference edge of the first sync signal leads or lags behind with respect to the reset pulse by comparing either the counted value of the second counter when the reference edge of the first sync signal is inputted or the counted value of the first counter when the reset signal generator generates the reset pulse with a predetermined threshold. If the mode discrimination circuit is outputting the first mode discrimination signal and the phase detector judges that the reference edge of the first sync signal is leading with respect to the reset pulse, the reference value Nr is set to a value not smaller than Nixe2x88x92Nj and not greater than the first value Ni. If the mode discrimination circuit is outputting the first mode discrimination signal and the phase detector judges that the reference edge of the first sync signal is lagging behind with respect to the reset pulse, the reference value Nr is set to a value not smaller than the first value Ni and not greater than Ni+Nj.
Further, the reset signal generator includes a state machine, a state of which is changed on the basis of the first value Ni; and the reference value Nr is determined on the basis of the state of the state machine.